I will bring a neuromorphic prototype chip with on-chip learning. The chip is called ALIVE, which stands for Always on Learning wIth Various synapsEs.

The ALIVE chip consists of two neural cores that implement two different dendritic error-based learning rules using multi-compartment neurons with several active dendritic branches. Both cores allow testing learning ideas in a single-layer network using errors. Each core has 4 neurons, and each neuron has 64 synapses (plastic and non-plastic). The two neural cores differ in the learning rule and in its circuit implementation. If anyone is interested, I would be happy to share more details.

All functional blocks have been tested and now I am in the process of testing the chip on network-level experiments. During the workshop, simple pattern classification tasks could be run to assess the performance of the chip.

In the context of few-shot learning/transfer learning, the ALIVE chip could be used as an output layer of an SNN trained offline for simple classification tasks compatible with the limited network capacity on the chip. Since the weights on the chip cannot be automatically configured (they all start from zero), I would like to find a scheme to do it by either using the learning on-chip or by coming up with some mapping for the plastic synapse stimulation. Simple transfer learning tasks could then be run on the chip and the effect of this “noisy” initialization/scheme could be assessed.

For this project, I would focus on one of the two neural cores, of which you can find more details at: Stochastic dendrites enable online learning in mixed-signal neuromorphic processing systems | IEEE Conference Publication | IEEE Xplore

Other suggestions or ideas are more than welcome and if anyone would like to play with this prototype neuromorphic chip I would be happy to help.